1. Field of the Invention
Example embodiments of the present invention relate generally to a latency control circuit and method thereof and an auto-precharge control circuit, and more particularly to a latency controlling circuit and a method of controlling latency and an auto-precharge control circuit.
2. Description of the Related Art
Data may be input to and/or output from a synchronous semiconductor device in synchronization with an external clock signal. Double data rate (DDR) dynamic random access memory (DRAM) may use a write latency (WL) scheme and/or an additive latency (AL) scheme to increase an efficiency of an address bus line or a command bus line.
If the latency scheme is used, after a number of clock cycles corresponding to latency have been counted, in response to a command received from a controller (e.g., a read or write command), an address signal may be activated for designating a memory address to/from which an internal command signal and/or data may be input/output. A circuit for delaying an external address signal or command signal by WL, AL, or (WL+AL) may further be included.
FIG. 24 is a circuit diagram illustrating a conventional latency control circuit 1500. Referring to FIG. 24, the conventional latency control circuit 1500 may include a plurality of registers 1511 through 1517 and a plurality of multiplexers 1521 through 1527, which may be connected to each other in series. A WL signal WLi (e.g., where I=1˜M) may be based on WL. For example, if WL is set to 7, only a signal WL7 may be activated (e.g., set to a first logic level, such as a higher logic level or logic “1”) and the remaining signals WLi, where I=1, 2, 3, 4, 5, 6, may be deactivated (e.g., set to a second logic level, such as a lower logic level or logic “0”). Accordingly, if the WL is 7, an address signal Ai may pass through the 7 registers 1511 through 1517 and then may be output as a delayed address signal CAi. Alternatively, if the WL is 4, the address signal Ai may pass through 4 registers 1511 through 1514 and then may be output as a delayed address signal CAi, and so on. Accordingly, after input latency (WL+AL), which may be caused due to an external command (e.g., a write command), a column address CAi for activating a column selection line may be generated. Therefore, a number of registers may be at least equal to the number of input latencies (AL+WL) for each bit of the address signal Ai. In an example, each register may be implemented by a flip-flop. Thus, a number of flip-flops may equal the number of input latencies within a circuit generating a bit of an address signal so that the circuit may be synchronized with an internal clock signal PCLK and may delay the address signals by desired latencies, thereby generating the column address CAi.
Because many flip-flops may be included in the conventional latency control circuit 1500, a current consumption may be relatively large. In addition, a higher-proportion of an available layout area may be reserved for the flip-flops within the conventional latency control circuit 1500.
With increases in operating frequencies (e.g., above 800 MHz in DDR-DRAM), AL and WL may increase to 10 or more. As a result, a number of registers required to perform latency control on an address and/or a command may likewise increase. For example, if AL is 8 and WL is 10 in a 512 Megabyte (MB) DDR synchronous DRAM (SDRAM), 18 registers (i.e., 8 registers for AL and 10 registers for WL) may be required for each bit of a 16-bit address signal. In addition, 8 registers for AL may be required for each command. Thus, if a total of 5 commands (e.g., /WE, /CS, /RAS, /CAS, and /OE) are externally received, a number of registers required for latency control on addresses and commands may be expressed by 18*16+8*5=248. If the number of registers increases above a threshold (e.g., 200 registers), an area occupied by the registers may increase and routing may become increasingly complicated. Further, the number of registers may further increase to accommodate for burst length. The burst length may refer to a number of bits which may be consecutively input or output per data input/output pin in response to a write or read command. In a conventional memory device (e.g., DDR2), in which two bits of data may be input or output per data input/output pin during a single clock cycle, an address may be delayed by a clock cycle corresponding to “burst length/2”, and therefore, at least a number of registers corresponding to the “burst length/2” may be required to output the single address signal. Accordingly, as the size of latency control circuit 1500 increases, a line or conductive path of a clock signal input to the latency control circuit 1500 may become longer, thereby increasing a delay time of the clock signal.
In order to quickly perform write and/or read operations, a semiconductor memory device, and particularly, a DRAM device, may perform a precharge operation for charging bit lines to a given voltage level to close an activated bank. The activated bank may be precharged before a new row in the activated bank may be opened. In other words, if data is written to or read from a memory cell through a bit line, the electric potential of the bit line may be changed. Accordingly, it may be necessary to precharge the bit line to the given voltage level after the data write or read operation.
A conventional precharge operation may be performed using a precharge command or an auto-precharge function. A precharge operation may also be performed after a write operation using a precharge command or an auto-precharge function. If the precharge command is issued after a write command to perform the precharge operation, a transmission efficiency of a data bus line may be decreased because an idle section (e.g., a portion on which no data may be transmitted through a bus line within a system) may occur. Accordingly, the auto-precharge function may typically be used to perform the precharge operation.
Typically, a write auto-precharge function may be performed in response to a write auto-precharge command, which may be defined by making a given signal (e.g., a bit A10 in an address signal), which may be input along with a write command applied from an external source (e.g., a memory controller), transition to the first logic level (e.g., a higher logic level or logic “1”).
Thus, if the given signal (e.g., the bit A10 in the address signal) is set to the first logic level and received along with the write command, DRAM may internally generate a write auto-precharge command and may perform a write auto-precharge operation. The write command may be first executed based on the generated write auto-precharge command. The precharge operation may not be performed until the last data in a burst write sequence is stored in a memory array in response to the write command. After a given period of time following the last data being stored in the memory array, the precharge operation may be performed.
The given period of time may be a write recovery time tWR (e.g., a minimum “wait time” before data may be written to the memory cell). In an example, the write recovery time tWR may be fixed at about 15 ns. Accordingly, the precharge operation may be performed after the write recovery time tWR. The write auto-precharge command may thereby have to be delayed.
FIG. 25 illustrates a conventional auto-precharge control circuit 2100 which delays a write auto-precharge command by the write recovery time tWR.
Referring to FIG. 25, the auto-precharge control circuit 2100 may be a circuit for controlling an auto-precharge operation of DDR3 DRAM, which may include 8 banks and may have an operating frequency of 1.6 GHz. Accordingly, because a clock signal applied to the DDR3 DRAM may have a frequency of 800 GHz and a cycle of 1.25 ns, an auto-precharge command may be delayed by 12 clock cycles of the clock signal, which may correspond to 15 ns of the write recovery time tWR.
Referring to FIG. 25, the auto-precharge control circuit 2100 may include a precharge sub-signal generator 2110 and a precharge main signal generator 2120. The precharge sub-signal generator 2110 may include a decoder 2111 and an AND element array 2112. The decoder 2111 may output first precharge sub-signals BANK0 through BANK7, which may respectively correspond to 8 banks, based on bank address signals dBA0 through dBA2. The AND element array 2112 may include 8 AND elements connected in parallel and may perform an AND operation on each of the first precharge sub-signals BANK0 through BANK7 and a write auto-precharge command signal dWAP to output second precharge sub-signals FAP0 through FAP7.
Referring to FIG. 25, the precharge main signal generator 2120 may include a plurality of register arrays, which may respectively delay the second precharge sub-signals FAP0 through FAP7 output from the precharge sub-signal generator 2110 and may output precharge main signals PAPB0 through PAPB7 to the banks, respectively. The precharge operation may be performed based on the precharge main signals PAPB0 through PAPB7.
Referring to FIG. 25, in order to delay the second precharge sub-signals FAP0 through FAP7 by the write recovery time tWR, each of the register arrays may include 12 registers connected in series, which may respond to an internal clock signal PCLK.
Accordingly, referring to FIG. 25, the number of registers included within the auto-precharge control circuit 2100 may be 96, which may be obtained by multiplying the number of banks (i.e., 8) by the number of clock cycles of the internal clock signal PCLK (i.e., 12) corresponding to the write recovery time tWR (e.g., 15 ns). As described above, the number of registers may be related to the number of banks and the cycle of a clock signal. With the increase of an operating frequency and the decrease of a cycle of a clock signal in a memory device, the number of clock cycles of the internal clock signal PCLK, which corresponds to the write recovery time tWR, may be increased. As a result, the number of registers required to execute a write auto-precharge command may be increased.
As the number of registers is increased, as well as an area occupied by the registers in a layout, loading of the internal clock signal PCLK, which may be input to each register, may also be increased. As a result, a power consumption or current consumption may be increased.